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February 1999 PRELIMINARY
ML6460 CCIR656 NTSC Video Encoder with Macrovision(R)
GENERAL DESCRIPTION
The ML6460 is a multi-standard CCIR656 (4:2:2) video (input) composite and S-video (outputs) encoder for NTSC systems. It is designed to provide a low cost, single-chip output interface for a variety of video applications including set-top decoders, DVD players, and other YCrCb to Y/C equipment. The ML6460 accepts 8-bit YCrCb video in either CCIR656 or Square Pixel format and generates analog Y, C and CV waveforms complete with Macrovision(R) copy protection technology and Closed Caption encoding. The ML6460 includes output analog reconstruction filters, phase equalizer, and 6dB (2X gain) drivers. Gain scaling, sync, and Y+C mixing are performed at the output of the relevant 10-bit DAC, eliminating the gain mapping stages that require additional DAC bits. The result is Y SNR and granularity remain precisely the same as the source. The ML6460 supports both master and slave timing operations. S-Video and multiple composite signals can be driven simultaneously into 75 loads.
FEATURES
s s s s s s
Macrovision(R) copy protection technology Closed Caption VBI encoder for line 21 and 284 Handles SAV/EAV codes for CCIR656 Video Single clock input: 27MHz CCIR656, 24.54MHz Sq. Pix. Color subcarrier correction for overlay applications Onboard analog 7th-order reconstruction filters and 6dB drivers with differential gain/phase of 0.5%/0.5 Y, C, CV outputs drive both AC or DC coupled loads Multiple 75 line drivers for two composite outputs, channel modulator, and S-Video 2-wire serial control bus, or selectable presets for standalone operation Handles Japanese NTSC signals
s s
s
s
BLOCK DIAGRAM
7
DVCC1 YCRCB0 DGNDI
8
14
DVCC2
15
DGND2 10 BIT YDAC
1
AVCC1
2
AGND1
25
AVCC2
24
AGND2 YOUT
21
YCRCB1
20
YCRCB2
LUMA BLANKING
DELAY COMPENSATION
UP SAMPLER
LUMA RECONSTRUCTION FILTER (FIR)
19
YCRCB3
7th ORDER ANALOG FILTER WITH GROUP DELAY EQUALIZATION
6dB
27
CVOUT
+
+
6dB
26
COUT
INPUT Y/C DEMUX & CLOCK GENERATOR
18
YCRCB4
6dB
28
17
YCRCB5
13
YCRCB6
12
YCRCB7
TIMING GENERATOR (SAV/EAV)
MACROVISION(R) COPY PROTECTION TECHNOLOGY CLOSED CAPTIONING
NEGATIVE SYNC DAC POSITIVE SYNC DAC REFERENCE GENERATOR
7th ORDER ANALOG FILTER WITH GROUP DELAY EQUALIZATION
11
CLK
16
VSYNC
9
HSYNC
10
FIELD
CHROMA BLANKING
BURST INSERTION
5
SCLK
COLOR SPACE CONVERTER
UP SAMPLER
CHROMA BANDLIMIT FILTER
MULTIPLYING ACCUMULATOR CHROMA RECONSTRUCTION FILTER (FIR)
UP SAMPLER
CDAC
22
SDATA
23
PRESET1
SERIAL INTERFACE
OVERLAY INTERFACE
PHASE ACCUMULATOR
SUBCARRIER GENERATION
8
PRESET0
PHERR
4
3
6
1
ML6460
PIN CONFIGURATION
ML6460 28-Pin SOIC (S28)
AVCC1 AGND1 PRESET0 PRESET1 FIELD PHERR DVCC1 DGND1 VSYNC HSYNC YCRCB7 YCRCB6 YCRCB5 DVCC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 COUT YOUT CVOUT AVCC2 AGND2 SDATA SCLK YCRCB0 YCRCB1 YCRCB2 YCRCB3 YCRCB4 CLK DGND2
TOP VIEW
2
ML6460
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2 3 4 5
AVCC1 AGND1 PRESET0 PRESET1 FIELD
Analog 5V supply pin Analog ground pin Preset input pin for stand alone operation Preset input pin for stand alone operation This pin can be configured as an input or output via the control register (bits B8 and B9). If configured as output, it can be programmed to give analog or digital (even/odd) field information. If configured as input, it can be used to set analog fields (1 and 2) or (3 and 4). External chroma lock input Digital 5V supply pin Digital ground pin Vertical synchronization signal. Pin is configured as input in external slave mode and as output in master and internal slave (CCIR656) modes. Polarity and function are programmed in control register in bits B10, B17, B26, and B28. Horizontal synchronization signal. Pin is configured as input in external slave mode and as output in master and internal slave (CCIR656) modes. Polarity and function are programmed in control register in bits B15, B25, B28, and B29.
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
YCRCB7 YCRCB6 YCRCB5 DVCC2 DGND2 CLK YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 SCLK SDATA AGND2 AVCC2 CVOUT YOUT COUT
YCRCB digital input bit 7 YCRCB digital input bit 6 YCRCB digital input bit 5 Digital 5V supply pin Digital ground pin System clock: 27Mhz (CCIR656 rate), 24.54Mhz (Square Pixel rate) YCRCB digital input bit 4 YCRCB digital input bit 3 YCRCB digital input bit 2 YCRCB digital input bit 1 YCRCB digital input bit 0 Serial control bus clock input Serial control bus data input Analog ground pin Analog 5V supply pin Composite video output Luma output Chroma output
6 7 8 9
PHERR DVCC1 DGND1 VSYNC
10
HSYNC
3
ML6460
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. AVCC, DVCC .................................................... -0.3 to 7V Analog and Digital Inputs/Outputs .. -0.3 to AVCC + 0.3V Input current per pin ................................... -25 to 25mA Storage Temperature .................................... -65 to 150C Junction Temperature .............................................. 120C
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C Operating Supply Range .............................. 4.5V to 5.5V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, AVCC = DVCC = 4.5V to 5.5V, TA = Operating Temperature Range (Note 1)
SYMBOL POWER PERFORMANCE Power Dissipation SUPPLIES AV CC DVCC ISA ISD Analog Supply Voltage Digital Supply Current Analog Supply Current Digital Supply Current Max. Programmed Clock Rates 4.5 4.5 125 35 5.5 5.5 V V mA mA 750 mW PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUT SIGNALS VIL VIH IIL IIH Input Low Voltage Input High Voltage Low Level Input Current High Level Input Current Input Capacitance DIGITAL OUTPUT SIGNALS VOL VOH Low Level Output Voltage High Level Output Voltage Output Capacitance ENCODER AND DAC (Note 2) Output Amplitude Accuracy CV Output Amplitude C Output Amplitude Y Analog/Digital Bandlimit C Analog/Digital Bandlimit Vector Phase Accuracy (Note 3) Vector Amplitude Accuracy (Note 3) Chroma Phase Linearity Chroma Amplitude Linearity Differential Gain Differential Phase SMPTE Color Bars SMPTE Color Bars, Peak-to-Peak SMPTE Color Bars, Peak-to-Peak Swept Multiburst Swept Multiburst Swept Multiburst SMPTE Color Bars NTC7 Stepped Subcarrier NTC7 Stepped Subcarrier NTC7 Modulated Staircase (Note 2) NTC7 Modulated Staircase (Note 2) -2.5 -2.5 -2 -1 0.5 0.5 0.95 0.594 5.7 1.5 1 2.5 2.5 2 1 1 1 2 5 1.05 0.657 % V V MHz MHz % IRE % IOUT = 2mA IOUT = 100A VCC-0.4 50 0.4 V V pF VIN = at 0.1V VIN = at DVCC - 0.1V 2 2.0 1 1 0.8 V V A A pF
4
ML6460
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER ENCODER AND DAC (Continued) (Note 2) Luma Nonlinearity FSC Phase Jitter (RMS) Quadrature Error SMPTE Color Bars SMPTE Color Bars -1 1 1 1 IRE
(Continued)
CONDITIONS MIN TYP MAX UNITS
SERIAL BUS
SYMBOL INPUT VIL V IH IIL IIH ZIN C IN Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Input Impedance Input Capacitance VIN = 0V VIN = DVCC fCLK = 100kHz 1 2 0 VCC - 0.8 0.8 V CC 1.0 1.0 V V A A M pF PARAMETER CONDITIONS MIN TYP MAX UNITS
SYSTEM TIMING fCLOCK VHYS tSPIKE t WAIT SCLK Frequency Input Hysteresis Spike Suppression Wait Time From STOP to START On SDATA Max Length for Zero Response 0.2 50 1.3 0.6 0.6 1.3 0.6 5.0 Fast mode Slow mode tLH tHL tSU/STOP Rise Time for SCLK & SDATA Fall Time for SCLK & SDATA Setup Time for STOP On SDATA 100 250 30 30 0.6 300 300 100 kHz V ns s s s s s s ns ns ns ns s
t HD/START Hold Time for START On SDATA tSU/START Setup Time for START On SDATA tLOW tHI Min LOW Time On SCLK Min HIGH Time On SCLK
t HD/DATA Hold Time On SDATA t SU/DATA Setup Time On
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: All specifications include reconstruction filter and line driver. Note 3: Normalized to burst.
5
ML6460
FUNCTIONAL DESCRIPTION
INTRODUCTION The ML6460 is a single-chip NTSC video encoder for generating analog composite (CV) and S-video (Y/C) outputs from YCrCb digital inputs. The ML6460 is a mixed signal processor optimizing SNR and distortion by performing subcarrier generation, sync generation, modulation and upsampling in the digital domain, while performing mixing, reconstruction and gain scaling in the analog domain. In particular, the Y channel requires no digital scaling, eliminating the need for higher precision digital solutions. All timing is based on an external clock source either 27MHz for CCIR656 clock rate or 24.54MHz for square pixel clock rate. Additionally, the ML6460 allows the inclusion of Closed Captioning codes in the vertical blanking interval (VBI). Both lines 21 and 284 support Closed Captioning. The ML6460 also incorporates Macrovision(R) copy protection technology. Other special functions include: programmable polarity and relative position of sync pulses, master and slave modes of which includes the ability to handle ITU-R656compliant digital TV or ITU-R/SMPTE specifications, chroma subcarrier phase and frequency adjustments from external source; Japanese NTSC support; 100% color bars processing; and internal 7th order reconstruction filters with group delay equalization and 6dB line drivers for direct TV output. The ML6460 can be programmed and controlled via a two-wire serial bus or preset modes. A summary of the features of the ML6460 are listed in Table 1. VIDEO STANDARDS SUPPORTED The ML6460 supports NTSC only. The video standards and clock rates are listed in Table 2.
DEVICE Video Formats
FUNCTIONAL DESCRIPTION Clock DAC Rates
Closed Caption Encoder
Macrovision
Reconstruction Filter
75 Cable Driver
NTSC
PAL
CCIR656
Square Pixel
ML6460
Yes. Input: 8-Bit YCrCb digital Outputs: Y, C, and CV analog Yes. Input: 8-Bit YCrCb digital Outputs: Y, C, and CV analog
No
Yes
Yes
Yes. 10-bit DAC Yes. 10-bit DAC
Yes
Yes
ML6461
No
Yes
Yes
Yes
No
Yes. 7th-order Butterworth, with group delay equalization Yes. 7th-order Butterworth, with group delay equalization
Yes.
Yes.
Table 1. Video Encoder Functional Selection
INPUT NTSC CCIR656 NTSC Square Pixel
CLOCK RATE 27 MHz 24.54 MHz
HORIZONTAL LINES PER FRAME 525 525
PIXELS PER HORIZONTAL LINE 858 780
Table 2: Video Standards and Clock Rates
MODE Master Mode External Slave Mode Internal Slave Mode (SAV/EAV CCIR656)
VSYNC PIN OUT IN OUT
HSYNC PIN OUT IN OUT
FIELD PIN IN/OUT IN/OUT IN/OUT
Table 3: Pin Assignments for Various Master/Slave Modes
6
ML6460
FUNCTIONAL DESCRIPTION
VIDEO TIMING AND INPUTS The clock source for the ML6460 can be either 27MHz (CCIR656) or 24.54MHz (NTSC Square Pixel). The ML6460 internal timing generator also provides necessary horizontal and vertical syncs, video blanking, burst, Macrovision(R) timing, and closed caption timing. The internal clock is derived through buffering and inverting the external CLK signal. The inputs YCRCB<7:0>, VSYNC, and HSYNC are registered at the rising edge of CLK and PHERR is registered at the falling edge of CLK. All inputs must be valid for the minimum setup time of 5ns. The outputs VSYNC, HSYNC, and FIELD are clocked at the rising edge of CLK and are valid 10ns following the edge of the clock. The ML6460 can operate in master and slave modes. In master mode, the ML6460 internally generates the vertical reset (VSYNC pin is an output) and horizontal reset (HSYNC pin is an output). In the slave modes, there are two alternatives. External slave mode allows the user to provide an external vertical reset (VSYNC pin is an input) and an external horizontal reset (HSYNC pin is an input). Internal slave mode (CCIR656) uses the SAV and EAV codes to generate the vertical and horizontal resets. The master/slave modes are selected via register program. Table 3 provides a description of the various modes and the assignments of the VSYNC, HSYNC, and FIELD pins. MASTER MODE A logical 0 in the SLAVE/MASTER bit (bit B28) will configure the ML6460 in the master mode. Multiplexed Y, Cr, Cb data is streamed through the YCRCB <7:0> input pins. VSYNC and HSYNC pins are configured as outputs and provide vertical and horizontal sync information. The polarity of the active edge of the HSYNC and VSYNC pulses can be programmed through the control register via the SENSE_HSYNC bit (bit B15) and the SENSE_VSYNC bit (bit B10), respectively. Coincident active edges of the horizontal and vertical syncs at the start of the line 4 indicates the beginning of an odd field, whereas, the active edge of the vertical sync pulse when the horizontal sync is non-active at the middle of line 266, indicates the beginning of an even field (Figure 1). The FIELD pin can be configured either as an input or output through the FRAME_MODE bit (bit B8). If configured as output (B8 =0) it can be set to provide either even/odd field information (B9 = FLD_FRM_MODE = 0) or analog field information (B9 = 1). For the former case, a logical 1 on the FIELD pin indicates odd fields and a logical 0 even fields. For the latter,(on the FIELD pin), a logical 1 is held during analog fields 1 and 2, and a logical 0 during analog fields 3 and 4. If the FIELD pin is configured as an input (B8 = FRAME_MODE = 1) it must be held low and high on alternating frames and it should change state at the beginning of vertical sync during fields 1 and 3. The internal subcarrier oscillator is reset to make the frame -- for which FIELD pin is held 1 -- correspond to analog fields 1 and 2 (Figure 2). In master mode, a composite blanking signal is also available thru the HSYNC pin.
(Continued)
This can be activated via the CBLANK bit (B29=1). The polarity of the composite blanking signal is programmable from the SENSE_HSYNC bit (B15). When the SENSE_HSYNC bit is set (B15=1), the ML6460 will output a logic 0 at the HSYNC pin during the pixels which are blanked. Conversely, when the SENSE_HSYNC bit is cleared (B15=0), the ML6460 will output a logic 1 at the HSYNC pin during the pixels which are blanked. Consequently, the YCRCB<7:0> inputs will be ignored and a constant blanking level will be output to the analog channels YOUT, COUT, and CVOUT. The operation of the VSYNC and FIELD pins are not affected by the settings of CBLANK and SENSE_HSYNC. SLAVE MODES A logical 1 in the SLAVE/MASTER bit (B28) will configure the ML6460 for slave mode. Based on what timing information is provided, there are two slave modes: internal and external. Composite blanking--similar to that described in Master Mode--is also available. Note that in the internal slave mode, vertical and horizontal sync pulses and/or composite blanking signals are output for monitoring purposes only. All timing is derived from SAV/ EAV codes. Internal Slave Mode for CCIR656 with SAV/EAV codes In this mode (B26 = SLAVE_MODE=1), all the horizontal and vertical timing information including odd/even field selection is embedded in the multiplexed Y, Cr, Cb data stream input through the YCRCB <7:0> pins. VSYNC and HSYNC pins are configured as outputs to give vertical and horizontal sync pulses respectively. The operation of the FIELD pin is similar to that in the master mode. Composite blanking -- similar to the one described in the master mode -- is also available. Note that in the internal slave mode, vertical and horizontal sync pulses and / or composite blanking signal is output for monitoring purposes only. As mentioned above, all timing is derived from SAV/EAV codes. External Slave Mode In this mode: Where (B26 = SLAVE_MODE=0), horizontal and vertical reset pulses must be provided externally through HSYNC and VSYNC pins which are configured as inputs. The polarity of these pulses is programmed through bits SENSE_HSYNC (B15) and SENSE_VSYNC (B10). A horizontal reset pulse on the HSYNC pin can be given either at the beginning of active video (B25=HRESET_MODE=1) or at the beginning of horizontal blanking (B25=HRESET_MODE=0). Once per frame, the active edge of a vertical reset pulse coincident with the active edge of a horizontal reset pulse initializes the internal vertical line counter to the beginning of an odd field at line 4. Non-coincident vertical reset pulses, for example, the ones which fall outside of the interval (see Figure 3) determined by the active edge of the horizontal reset pulse, will be ignored. The FIELD pin, as explained above can be configured as an input to dictate analog
7
ML6460
FUNCTIONAL DESCRIPTION
(Continued)
vertical reset pulse unconditionally resets the vertical line counter to line 4. For proper operation only one active edge should be sent per frame. The polarity is controlled by SENSE_VSYNC (B10). fields or as an output to monitor odd/even fields or analog fields (1-2) and (3-4). The ML6460 also supports a frame based synchronization mode (B17 = FSYNC = 1) where a
Line 3 HSYNC
Line 4
Line 5
Line 6
Coincident Active Edges VSYNC
Beginning of an Odd Field
Line 265 HSYNC
Line 266
Line 267
Line 268
Line 269
VSYNC
Beginning of an Even Field
Figure 1. Example of the Beginning of the Odd And Even Fields vs. HSYNC and VSYNC in Master Mode. (SLAVE/MASTER = 0, SENSE_HSYNC = 0, SENSE_VSYNC = 0)
8
ML6460
H FIELD (1,2 and 3,4) L H FIELD (ODD/EVEN) L ANALOG FIELD 1 SERRATION PULSES
523
524
525
1
2 EQUALIZING PULSES
3
4
5 BURST PHASE
6
7
8 EQUALIZING PULSES
9
10
22
H FIELD (1,2 and 3,4) L H FIELD (ODD/EVEN) L ANALOG FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
285
286
H FIELD (1,2 and 3,4) L H FIELD (ODD/EVEN) L ANALOG FIELD 3 START OF VSYNC
523
524
525
1
2
3
4
5 BURST PHASE
6
7
8
9
10
22
H FIELD (1,2 and 3,4) L H FIELD (ODD/EVEN) L ANALOG FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
285
286
Figure 2. Four Fields (M) NTSC Format FIELD Pin Out
9
ML6460
FUNCTIONAL DESCRIPTION
PIXEL SYNCHRONIZATION Master Mode In this mode, the active edge of horizontal sync pulse through the HSYNC pin (configured as an output) indicates the beginning of an active video line (or the beginning of the horizontal blanking) and the multiplexed YCrCb pixel data must be synchronized to
(Continued)
this edge for proper video location, as well as the proper demultiplexing of YCrCb values. This synchronization, as shown in Figures 4 through 5a, is controlled by SEL_HSYNC1 (B14) and SEL_HSYNC0 (B13). Figures 4 and 4a show synchronization for active edge at the beginning of active video for positive or negative HSYNC polarity while Figures 5 and 5a show synchronization for active edge at the beginning of horizontal blanking for positive or negative HSYNC polarity.
H FIELD (1,2 and 3,4) L H FIELD (ODD/EVEN) L ODD EVEN ODD EVEN ODD EVEN ANALOG FIELDS 1 & 2 ANALOG FIELDS 3 & 4 ANALOG FIELDS 1 & 2
Figure 2a. FIELD Pin Output Summary
active edge of HSYNC HSYNC
active edge of VSYNC VSYNC
-32 pixels
64 pixels
coincident interval for HRESET_MODE=0
active edge of HSYNC HSYNC
VSYNC
active edge of VSYNC
64 pixels coincident interval for HRESET_MODE=1
Figure 3. Coincident Valid Sync Intervals for External Slave Mode
10
ML6460
CLK (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) HSYNC (output) (0,0) (0,1) (1,0) (1,1)
YCrCb
BL
BL
BL
BL
BL
CB0
Y0
CR0
Y1
CB2
Y2
CR2
Y3
Beginning of Active Line
T
2T
3T
Selectable Delay Synchronization
Figure 4. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Active Video. (CBLANK = 1, SENSE_HSYNC = 0) (BL = Blanked Pixel)
CLK (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) HSYNC (output) (0,0) (0,1) (1,0) (1,1)
YCrCb
BL
BL
BL
BL
BL
CB0
Y0
CR0
Y1
CB2
Y2
CR2
Y3
Beginning of Active Line
T
2T
3T
Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0)
Figure 4a. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Active Video. (CBLANK = 1, SENSE_HSYNC = 1) (BL = Blanked Pixel)
11
ML6460
CLK (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) HSYNC (output) (0,0) (0,1) (1,0) (1,1)
YCrCb
BL T 2T
BL 3T
BL
BL
BL
BL
CB0
Y0
CR0
Y1
Beginning of Horizontal Blanking
Q Clock Cycles # of Clock Cycles, Q if SELCCIR = 1 if SELCCIR = 0 244 214 252 214
if ANALOG_HBLANK = 0 if ANALOG_HBLANK = 1
Figure 5. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Horizontal Blanking. (CBLANK = 0, SENSE_HSYNC = 0) (BL = Blanked Pixel)
CLK (0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0) HSYNC (output) (0,0) (0,1) (1,0) (1,1)
YCrCb
BL T 2T
BL 3T
BL
BL
BL
BL
CB0
Y0
CR0
Y1
Beginning of Horizontal Blanking
Q Clock Cycles # of Clock Cycles, Q if SELCCIR = 1 if SELCCIR = 0 244 214 252 214
if ANALOG_HBLANK = 0 if ANALOG_HBLANK = 1
Figure 5a. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Horizontal Blanking. (CBLANK = 0, SENSE_HSYNC = 1) (BL = Blanked Pixel)
12
ML6460
FUNCTIONAL DESCRIPTION
Internal Slave Mode Embedded in the YCrCb data stream, the timing code 0xFF, 0x00, 0x00, 0x(SAV) must be inserted before the samples of the first active pixel. Figures 6 through 6b illustrate timing for CCIR656 video with SAV and EAV codes for CCIR or Square Pixel clocking. External Slave Mode A horizontal reset pulse can be used either at the beginning of active video or the beginning of horizontal blanking to provide synchronization of the YCrCb data to the internal clock. Bits SEL_HSYNC1(B14) and SEL_HSYNC0 (B13) are provided to achieve some degree of programmability in this synchronization. Figures 7 and 7a show synchronization for active edge at the beginning of active video for positive or negative HSYNC polarity while Figures 8 and 8a show synchronization for active edge at the beginning of horizontal blanking for positive or negative HSYNC polarity. Polarity of HSYNC and VSYNC In both the Master and Slave modes, the HSYNC and VSYNC polarity can be selected via bit SENSE_HSYNC and SENSE_VSYNC. When the SENSE_HSYNC bit is set to logical 1, the HSYNC pulse is on the rising edge. When the SENSE_HSYNC bit is cleared to logical 0, the HSYNC pulse is on the falling edge. Similarly, when the SENSE_VSYNC bit is set logical 1, the VSYNC pulse is on the rising edge.
(Continued)
When the SENSE_VSYNC bit is cleared to logical 0, the VSYNC pulse is on the falling edge. HSYNC Timing Delay In both Master and Slave modes, the SEL_HSYNC1(B14) and SEL_HSYNC0 (B13) bits of the control register can be programmed to delay the HSYNC active edge up to three clock periods, 3T, where T is one period of the clock. CHROMA AND LUMA PROCESSING Refer to Figures 9 through 12. VIDEO OUTPUT STAGE Reconstruction filtering, clamping, and line drivers The ML6460 can simultaneously provide outputs for Svideo, two composite video, and a TV modulator. Differential gain and phase are guaranteed at the outputs of the line drivers. Two internal 7th-order Butterworth filters and a group delay equalizer are used as reconstruction filters on S-video (NTSC). The composite signal is generated after reconstruction. The S-video (Y and C) and composite video (CV) are then fed into 75 line drivers. Each of the filter/drivers are designed to guarantee a differential phase of 0.5 and differential gain of 0.5%.
01234567 F00E8181 F00A0000 V BLANKING
*******
270
272
274
276
278
280
282
*******
1711
1713
1715
81F 00SCYCYCYCY B R 00F00AB R V ACTIVE LINE
YCYCY B R
4
268
4
1440
CB0
Y0
CR0
Y1
CB1
Y2
CR1
Y3
CB2 Y4
*******
Y715 CB358 Y716 CR358 Y717 CB359 Y718 CR359 Y719
ACTIVE
In CCIR format, there are
{}
720 Y 360 Cb 360 Cr
1440 in the active portion of a line.
LINE
Figure 6. CCIR Format: CLK = 27MHz
13
ML6460
01234567 F00E8181 F00A0000 V BLANKING 276 278 280 282 284 286 288 1555 1557 1559
*******
*******
81F 00SCYCYCYCY B R 00F00AB R V ACTIVE LINE
YCYCY B R
4
272
4
1280
CB0
Y0
CR0
Y1
CB1
Y2
CR1
*******
Y634 CR317 Y635 CB318 Y636 CR318 Y637 CB319 Y638 CR319 Y639
ACTIVE
In SQPIX format, there are
{}
640 Y 320 Cb 320 Cr
1280
LINE
in the active portion of a line.
Figure 6a. Square Pixel (SQPIX) Format: CLK = 24.54MHz
EAV and SAV Code Format (8-bits) 1 F V H P3 P2 P1 P0
SYNCHRONIZATION BITS
PROTECTION BITS (IGNORED BY ML6460) Format <1,F,V,H,P3,P2,P1,P0>
Line Number
Code SAV
1 1 1 1 1 1 1 1 1 1 1 1 1
F 1 1 0 0 0 0 0 0 1 1 1 1
V 1 1 1 1 0 0 1 1 1 1 0 0
H 1 0 1 0 1 0 1 0 1 0 1 0
P3~P0 X X X X X X X X X X X X
1 to 3 EAV 4 to 19 EAV SAV 20 to 263 EAV SAV 264 to 265 EAV SAV 266 to 282 EAV SAV 283 to 525 EAV SAV
Figure 6b. SAV/EAV Codes for 525/60.
14
ML6460
CLK
HSYNC (input)
YCrCb
BL
BL
A
B
C
D
E
F
G
H
Beginning of Active Line Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0) Value (SEL_HSYNC1, SEL_HSYNC0) (0,1) (0,0) (1,1) (1,0) BL CB0 BL BL CB0 Y0 BL BL Y0 CR0 BL CB0 CR0 Y1 CB0 Y0 Y1 CB2 Y0 CR0 CB2 Y2 CR0 Y1 Y2 CR2 Y1 CB2 CR2 Y3 CB2 Y2
Bit
A B C D E F G H
Figure 7. Pixel Synchronization. For External Mode, Active Edge at Beginning of Active Video. (HRESET_MODE = 1, SENSE_HSYNC = 0, BL = Blanked Pixel) (ANALOG_HRESET = ANALOG_HBLANK = 0 OR ANALOG_HRESET = ANALOG_HBLANK = 1)
CLK
HSYNC (input)
YCrCb
BL
BL
A
B
C
D
E
F
G
H
Beginning of Active Line Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0) Value (SEL_HSYNC1, SEL_HSYNC0) (0,1) (0,0) (1,1) (1,0) BL CB0 BL BL CB0 Y0 BL BL Y0 CR0 BL CB0 CR0 Y1 CB0 Y0 Y1 CB2 Y0 CR0 CB2 Y2 CR0 Y1 Y2 CR2 Y1 CB2 CR2 Y3 CB2 Y2
Bit
A B C D E F G H
Figure 7a. Pixel Synchronization. For External Mode, Active Edge at Beginning of Active Video. (HRESET_MODE = 1, SENSE_HSYNC = 1, BL = Blanked Pixel) (ANALOG_HRESET = ANALOG_HBLANK = 0 OR ANALOG_HRESET = ANALOG_HBLANK = 1)
15
ML6460
CLK
HSYNC (input)
YCrCb
BL
BL
A
B
C
D
E
F
G
H
Beginning of Horizontal Blanking
P Clock Cycles
Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0) Value (SEL_HSYNC1, SEL_HSYNC0) (0,1) (0,0) (1,1) (1,0) BL CB0 BL BL CB0 Y0 BL BL Y0 CR0 BL CB0 CR0 Y1 CB0 Y0 Y1 CB2 Y0 CR0 CB2 Y2 CR0 Y1 Y2 CR2 Y1 CB2 CR2 Y3 CB2 Y2
# of Clock Cycles, P if SELCCIR = 1 if SELCCIR = 0 244 220 If ANALOG_HBLANK = 0 252 220 If ANALOG_HBLANK = 1
Bit
A B C D E F G H
Figure 8. Pixel Synchronization. For External Mode, Active Edge at Beginning of Horizontal Blanking. (HRESET_MODE = 0, SENSE_HSYNC = 0, BL = Blanked Pixel)
CLK
HSYNC (input)
YCrCb
BL
BL
A
B
C
D
E
F
G
H
Beginning of Horizontal Blanking
P Clock Cycles
Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0) Value (SEL_HSYNC1, SEL_HSYNC0) (0,1) (0,0) (1,1) (1,0) BL CB0 BL BL CB0 Y0 BL BL Y0 CR0 BL CB0 CR0 Y1 CB0 Y0 Y1 CB2 Y0 CR0 CB2 Y2 CR0 Y1 Y2 CR2 Y1 CB2 CR2 Y3 CB2 Y2
# of Clock Cycles, P if SELCCIR = 1 if SELCCIR = 0 244 220 If ANALOG_HBLANK = 0 252 220 If ANALOG_HBLANK = 1
Bit
A B C D E F G H
Figure 8a. Pixel Synchronization. For External Mode, Active Edge at Beginning of Horizontal Blanking. (HRESET_MODE = 0, SENSE_HSYNC = 1, BL = Blanked Pixel)
16
ML6460
10 0
0 1
-10 -20 (dB) -30 -40
-3 -1
(dB)
-2
-50 -60
-4
0
1
2
3
4
5
6
7
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 9. Chroma Bandlimit Filter: Stopband (FIR Filter)
Figure 10. Chroma Bandlimit Filter: Passband (FIR Filter)
ANALOG RECONSTRUCTION FILTER DIGITAL FIR FILTER TOTAL FILTER AND BUFFER RESPONSE
DIGITAL FIR FILTER TOTAL FILTER AND BUFFER RESPONSE
10 0 -10 -20
(dB) (dB)
1 0 -1 -2 -3 -4 -5 -6
-30 -40 -50 -60
1
5
10
15
20
25
30
0
1
2
3
4
5
6
7
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 11. Reconstruction Filter: Stopband (Normalized)
Figure 12. Reconstruction Filter: Passband (Normalized)
17
ML6460
FUNCTIONAL DESCRIPTION
(Continued)
needed per frame. If both lines are used for transmission, then four bytes (the first two bytes corresponding to line 21) must be entered all at once into the closed caption data register (CC register). 3. Set the control register bits CC_21 (B19) and/or CC_284 (B18) to logical 1. This will enable CC transmission at the desired lines. 4. Repeat STEP 2 as many times as needed. Note that CC data is transmitted once (twice if both lines are used) per frame. Hence attempts to transmit CC data at a rate faster than four bytes per frame will result on overwriting some of the previously entered data before the encoder has a chance to transmit. To prevent overwriting of data, the CC controller and the ML6460 need to be synchronized. This can be easily achieved by polling the vertical blanking pulse and updating the CC data registers once per frame during the vertical blanking interval or any appropriate interval which does not include lines 21 or 284. Also, active video information is blanked on lines for which closed caption transmission is enabled. Note that the last data written on the CC registers will be sent continuously once per frame (on line 21 or line 284 depending on the mode chosen) until the interface is disabled. Figure 13 shows Closed Caption waveforms for various modes. See Table 7 and Figure 17 for more Closed Caption information. Note that parity bits A7, A15, A23, and A31 must be generated externally. PROGRAMMING INTERFACE The ML6460 can be programmed either through PRESET modes or through SERIAL BUS mode. REGISTER INFORMATION See Table 6 for ML6460 register summary information. CONTROL REGISTERS: DESCRIPTION OF FUNCTION Reserved, B31:B30 These bits are reserved and must be set to 0 (B31=B30=0) for normal operation. CBLANK, B29 In master mode, and internal slave mode, a composite blanking signal is also available thru the HSYNC pin. This can be activated via the CBLANK bit (B29=1). The polarity of the composite blanking signal is programmable thru the SENSE_HSYNC bit (B15). When the SENSE_HSYNC bit is set (B15=1), the ML6460 will output a logic 0 at the HSYNC pin during the pixels which are blanked. Conversely, when the SENSE_HSYNC bit is cleared (B15=0), the ML6460 will output a logic 1 at the HSYNC pin during the pixels which are blanked. Consequently, the YCRCB<7:0> inputs will be ignored and a constant blanking level will be output to the analog channels YOUT, COUT, and CVOUT. The operation of the VSYNC and FIELD pins are not affected by the settings of CBLANK and SENSE_HSYNC. PHASE ERROR INPUT AND CHROMA SUBCARRIER CORRECTION (FOR OVERLAY APPLICATIONS) The chroma oscillator phase and frequency can be altered in real time using the PHERR input. This pin can receive a signal that corrects chroma variations for signals with unstable time base errors. To properly initialize the ML6460 overlay interface, follow the steps below: 1. Set the control register bit OVERLAY_ON (B16) to logical 0. This will disable the interface and let the chroma subcarrier oscillator run free. 2. Force the PHERR input to logical 0 (idle state) for at least 128 clock cycles and set the control register bit OVERLAY_ON (B16) to logical 1 while PHERR is held low. This will enable the interface. 3. Clock in the startup code of 101 and then serially (LSB first) the 32-bit frequency value FSQ (frequency number) followed by the 12-bit phase value PHQ (phase number). Equation 1 calculates color subcarrier frequency:
FSC = FSQ 2
32
x
FCLK 2
(1)
Where FCLK is the 27 MHz (or 24.54MHz) as the system clock and FSC is the actual color subcarrier frequency. 4. To turn-off the interface and have the subcarrier oscillator on free run, the control register bit OVERLAY_ON (B16) must be reset to logical 0. 5. When this function is disabled, the internal default values for FSQ are: 0X 43E0F7AD for CCIR656 0X 4AAAAA0B for Square Pixel MACROVISION(R) COPY PROTECTION The ML6460 supports Macrovision(R) Copy Protection Process Revision 7.01. The process can be controlled via two-wire serial bus. For more information contact Macrovision Corporation. CLOSED CAPTIONING The ML6460 enables the transmission of VBI Closed Caption codes on lines 21 and 284. To properly initialize the closed caption interface, follow the steps below: 1. Set the control register bits CC_21 (B19) and CC_284 (B18) to logical 0. This will disable transmission of Closed Caption (CC) data. 2. For each line, write the two byte closed caption (CC) data, including the parity bit, to the CC data register through the serial bus interface. Note that the ML6460 does not generate the parity bits. If only line 21 or line 284 transmission is desired, only two bytes of data are
18
ML6460
FUNCTIONAL DESCRIPTION
(Continued)
SLAVE_MODE, B26 This bit determines the choice of two slave modes: internal slave mode or external slave mode. In internal slave mode (B26=1), horizontal and vertical timing information is embedded in the YCrCb data (via SAV / EAV codes); while the HSYNC and VSYNC pins can be used as outputs. In external slave mode (B26=0), horizontal and vertical sync pulses must be provided for timing and synchronization;in this case HSYNC and VSYNC pins are inputs. See Table 3. HRESET_MODE, B25 This bit determines whether the HSYNC is given at the beginning of active video (B25=1) or HSYNC is given at the beginning of blanking (B25=0). This bit (B25) is only available for external slave modes. SLAVE/MASTER, B28 This bit determines if device operates in master or slave modes. Configuration of HSYNC, VSYNC and FIELD are determined upon selection of this bit. Table 3 provides a summary of Slave / Master modes. When this bit is set (B28=1), the ML6460 is in slave mode. When this bit is cleared (B28=0), the ML6460 is in master mode. Special note for slave modes: this bit (B28) along with the SLAVE_MODE bit (B26) selects between internal (B26=1) and external slave modes (B26=0). SELCCIR, B27 This bit determines the frequency of choice between CCIR656 clock rate(27MHz) and Square Pixel clock rate (24.54MHz). When this bit is set (B27=1), CCIR656 clock rate is selected. When this bit is cleared (B27=0), the Square Pixel clock rate is selected.
10.5 0.25s 12.91s 7 CYCLES 3.58MHz COLOR BURST TWO: 7 BIT + PARITY BIT S T A A0 ~ A6 A7 A8 ~ A14 A15 R T 3.58MHz COLOR BURST
10.5 0.25s
12.91s 7 CYCLES TWO: 7 BIT + PARITY BIT S T A A0 ~ A6 A7 A8 ~ A14 A15 R T
50 2 IRE BLANK LEVEL 40 IRE SYNC LEVEL
50 2 IRE BLANK LEVEL 40 IRE SYNC LEVEL
LINE 21
LINE 284
10.003 0.25s 27.382s 33.764s
10.003 0.25s 27.382s 33.764s
Closed Caption on Line21 [CC_21 = 1 and CC_284 = 0]
10.5 0.25s 12.91s 7 CYCLES 3.58MHz COLOR BURST TWO: 7 BIT + PARITY BIT S T A A0 ~ A6 A7 A8 ~ A14 A15 R T
Closed Caption on Line284 [CC_21 = 0 and CC_284 = 1]
10.5 0.25s 12.91s 7 CYCLES 3.58MHz COLOR BURST TWO: 7 BIT + PARITY BIT S T A A16 ~ A22 A23 A24 ~ A30 A31 R T
50 2 IRE BLANK LEVEL 40 IRE SYNC LEVEL
50 2 IRE BLANK LEVEL 40 IRE SYNC LEVEL
LINE 21
LINE 284
10.003 0.25s 27.382s 33.764s
10.003 0.25s 27.382s 33.764s
Closed Caption on Line21 and Line 284 [CC_21 = 1 and CC_284 = 1] Figure 13. Closed Caption on Line 21 and Line 284.
19
ML6460
FUNCTIONAL DESCRIPTION
(Continued)
ANALOG_HRESET, B23 This bit is active only in external slave mode and when the external sync is given at the beginning of active video. In this mode, ANALOG_HRESET (B23) must be used in conjunction with ANALOG_HBLANK (B23) to choose between "analog" and digital" line encoding. The possible approaches are summarized in Table 4 below.. FULL_BAR, B22 This bit is used to program the ML6460 to encode in normal modes or 100% amplitude video (100% color bar). When this bit is set (B22=1), the ML6460 is ready to handle 100% color bars. With 75% amplitude signals, this bit should be cleared (B22=0) for optimum signal to noise performance. JAPAN_BLANK, B21 This bit is used to program the ML6460 to encode Japanese NTSC by removing the 7.5 IRE setup in blanking and thus boosting the gain of luma and chroma DACs. This bit is set (B21=1) to handle Japanese NTSC modes. ANALOG_HBLANK, B24 This bit determines whether the ML6460 is to encode for ITU_R656_compliant "digital" or ITU_/SMPTE_compliant "analog" encoding specifications. When this bit is cleared (B24=0), the ML6460 is optimized for full "digital" line encoding, where the number of active pixels is 720 for CCIR656 rates and 640 for square pixel rates. No tapering (edge smoothing) is done to the beginning and end of the active portion of the line. When this bit is set (B24=1), the ML6460 is optimized for "analog" line encoding, where the number of active pixels is 712 for CCIR656 rates and 640 for square pixel rates. The beginning and end of the active video portion of the line is tapered (smoothed) to minimize ringing introduced due to fast transitions. Figure 14 below illustrates the timing comparisons. Note: For the square pixel rate the only difference between "analog" and "digital" encoding is the tapering (smoothing) at the beginning and end of the active video portion of the line. The number of pixels encoded during the active video portion is the same in both cases. The positioning of the active portion is the same as in "analog" line encoding.
5.3s
9 CYCLES
4.7s CCIR656 DIGITAL LINE ENCODING: 720 PIXELS, 1440 TCLKs 1.56s 9s 9s + 4 PIXELS CCIR656 ANALOG LINE ENCODING: 712 PIXELS, 1424 TCLKs SQUARE PIXEL ANALOG AND DIGITAL ENCODING: 640 PIXELS, 1280 TCLKs
Figure 14. Timing of Horizontal Blanking Interval and Active Video ANALOG_ HRESET B23 0 0 1 1 ANALOG_ HBLANK B24 0 1 0 1 RECOMMENDED ENCODING ITU-R656 Digital TV Line Optional Not Recommended ITU-R/SMPTE Analog TIME BETWEEN H_SYNC AND ACTIVE VIDEO 9s 9s + 4pixels = 9.3s PIXELS ENCODED CCIR 656 SQUARE PIXEL 720 712
See Note 1
EDGE SMOOTHING (B24 = 1) none Yes
640 640
9s + 4pixels = 9.3s
712
See Note 2
640
Yes
Note 1: Ignore first four and last four pixels. Note 2: Ignore last eight pixels.
Table 4. Video Encoding Standards and Horizontal/Active Video Timing
20
ML6460
FUNCTIONAL DESCRIPTION
(Continued)
SWITCH_FIELD, B11 This bit is used to switch even/odd fields when set (B11=1). This bit is cleared (B12=0) for normal operation. This bit is only active in internal slave mode. SENSE_VSYNC, B10 This bit selects the polarity of the VSYNC active edge to a rising edge (if B10=1) or a falling edge (if B10=0). In internal slave modes VSYNC is configured as an output to be used for monitoring purposes. The polarity is still affected by this bit. FLD_FRM_MODE, B9 When set (B9=1), it causes the ML6460 FIELD pin to give analog field information if the FIELD pin is configured as an output (see B8). When cleared (B9=0), it causes the field pin to give odd/even field information if the FIELD pin is configured as an output (see B8). FRAME_MODE, B8 This bit configures the FIELD pin of the ML6460 as an input (if B8=1) or as an output (if B8=0). YDEL1, B7 This bit, in conjunction with YDEL0 (B6), is used to select luma delay in order to align luma and chroma data. See Table 5. YDEL0, B6 This bit, in conjunction with YDEL1 (B7), is used to select luma delay in order to align luma and chroma data. See Table 5. BURST_ON, B5 When active (B5=1) this bit provides burst at all times for testing purposes only. For normal operation this bit is cleared (B5=0). ACTIVE_ON, B4 When active (B4=1) this bit eliminates horizontal and vertical blanking intervals. Burst is suppressed. For testing purposes only. For normal operation this bit is cleared (B4=0). FIX_SCH, B3 When active (B3=1) this bit maintains SCH phase. In this condition known as a "coherent subcarrier" such that the subcarrier has a known phase relative to the active edge of HSYNC pulse. When this bit is cleared (B3=0), the subcarrier generation block is in free run mode. This condition is known as "incoherent subcarrier" where the phase of the subcarrier relative to the HSYNC is not fixed. CC_ALL, B2 When active (B2=1) this bit enables closed caption transmission on every line. For testing purposes only. For normal operation this bit is cleared (B2=0) and closed caption is enabled through control register bits CC_21 (B19) and CC_284 (B18). SUBCARRIER_OFF, B1 When active (B1=1) this bit disables the internal subcarrier oscillator. Used for test purposes only. For normal operation this bit is cleared (B1=0). AC_DC, B0 This bit configures the output buffers for AC coupled drive (if B0=1) and DC couple drive (if B0=0). WIDE_VBLANK, B20 Determines which lines to blank at the beginning of each field. For wide blanking, this bit is set (B20=1), the ML6460 provides 15 lines of blanking. For narrow blanking, this bit is cleared (B20=0), the ML6460 provides 9 lines of blanking. CC_21, B19 This bit enables (B19=1) and disables (B19=0) the transmission of closed captioning data on line 21. CC_284, B18 This bit enables (B18=1) and disables (B18=0) the transmission of closed caption data on line 284. FSYNC, B17 This bit enables (B17=1) and disables (B17=0) frame syncing. OVERLAY_ON, B16 This bit enables (B16=1) and disables (B17=0) the PHERR pin to be used as an interface to set the internal subcarrier oscillator's phase and frequency. SENSE_HSYNC, B15 This bit selects the polarity of the HSYNC active edge to a rising edge (if B15=1) or a falling edge (if B15=0). This bit is active in master modes or in external slave modes. In internal slave modes HSYNC is configured as an output to be used for monitoring purposes. The polarity is still affected by this bit. SEL_HSYNC1, B14 This bit, in conjunction with SEL_HSYNC0 (B13), is used to facilitate pixel synchronization. Figures 4, 5, 7, and 8 provide a detailed description. This bit is only active in master modes or in external slave modes. This bit is de-activated in internal slave modes. SEL_HSYNC0, B13 This bit, in conjunction with SEL_HSYNC1 (B14), is used to facilitate pixel synchronization. Figures Figures 4, 5, 7, and 8 provide a detailed description. This bit is only active in master modes or in external slave modes. This bit is de-activated in internal slave modes. SWITCH_UV, B12 This bit is used to switch Cr and Cb internally when set (B12=1). This bit is cleared (B12=0) for normal operation. This bit is intended for debug purposes only. If used, there may be some slight artifacts at the end of active line. YDEL1 (B7) 0 0 1 1 YDEL0 (B6) 0 1 0 1 OPERATION Normal Delay Luma Channel by 1 TCLK Advance Luma Channel by 1 TCLK Advance Luma Channel by 2 TCLK
Table 5. Luma Delay Selection
21
ML6460
DATA BIT B0 B1 B2 NAME AC_DC SUBCARRIER_OFF CC_ALL FIX_SCH ACTIVE_ON BURST ON YDEL0 YDEL1 FRAME_MODE FLD_FRM_MODE SENSE_VSYNC SWITCH_FIELD SWITCH_UV SEL_HSYNC0 SEL_HSYNC1 SENSE_HSYNC OVERLAY_ON FSYNC CC_284 CC_21 WIDE_BLANK JAPAN_BLANK FULL_BAR ANALOG_HRESET ANALOG_HBLANK HRESET_MODE SLAVE_MODE SELCCIR SLAVE/MASTER CBLANK Reserved Reserved DESCRIPTION Configures analog output buffers for AC or DC drive Disable internal subcarrier oscillator - for test only Enables Closed Caption transmission on every line Enable reset of subcarrier oscillator every other frame to maintain SCH phase Eliminate H & V intervals, suppress burst -- for test only Burst Available at all time -- For test only Delay/Advance luma channel Delay/Advance luma channel Configure FIELD pin as input or output Configure FIELD pin to give odd/even or 1,2 and 3,4 info Set vertical reset pulse polarity Switches even/odd fields Switch Cr and Cb internally Used to facilitate pixel synchronization Used to facilitate pixel synchronization Set horizontal reset pulse polarity Enables use of PHERR pin Enable frame syncing Enable transmission of Closed Caption data on line 284 Enable transmission of Closed Caption data on line 21 Select wide or narrow blanking Removes 7.5 IRE setup in blanking and boosts Y & C gain To handle 100% amplitude video (100% colorbars) Selects position of horizontal reset Select analog blanking with smooth transition at the edges or digital blanking Select H reset at start of active video or start of H blanking Select external H/V reset or embedded H/V reset Select CCIR656 rate or Square Pixel rate Select slave or master mode Composite Blanking Set to 0 for Proper Operation Set to 0 for Proper Operation BIT CODE RANGE 0 = DC, 1 = AC 0 = Normal, 1= Disable oscillator 0 = Normal, 1 = Enable 0 = Not reset, 1 = Oscillator reset 0 = Normal, 1 = Test Mode 0 = Normal, 1 = Test Mode = 00 = Normal = 01= Delay luma 1 clock cycle = 10 = Advance luma 1 clock cycle, = 11= Advance luma 2 clock cycles 0 = output, 1= input 0 = odd/even, 1= 1,2 or 3,4 0 = Falling edge, 1= Rising edge 0 = Normal, 1= switch even/odd 0 = Normal, 1= Switch Cr & Cb See Figures 4, 5, 7, 8 See Figures 4, 5, 7, 8 0 = Falling edge, 1= Rising edge 0 = Disable, 1= Enable PHERR pin 0 = Disable, 1= Enable 0 = Disable, 1= Enable transmission 0 = Disable, 1= Enable transmission 0 = 9 lines of blanking, 1= 15 lines 0 = Normal, 1= Japanese NTSC
0 = Normal, 1 handles 100%Amp. Video
LOWER BYTE LOWER MIDDLE BYTE UPPER MIDDLE BYTE
B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25
0 = Digital H blank edge, 1= Analog H blank edge 0 = Digital blanking, 1= Analog blanking 0 = Start of blanking, 1= Start of active
0=External H/V reset (H/V ext. source) 1=Embedded H/V reset (SAV/EAV codes)
UPPER BYTE
B26 B27 B28 B29 B30 B31
0 = Square Pixel, 1= CCIR656 0 = Master mode, 1= Slave mode 0 = Disable, 1= Enable
Note: B31 is MSB
Table 6: Control Register (CNTR) Summary
22
ML6460
DATA BIT A0 A1
NAME CC0 CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC13 CC14 CC15 CC16 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31
DESCRIPTION Closed Caption bit 0 Closed Caption bit 1 Closed Caption bit 2 Closed Caption bit 3 Closed Caption bit 4 Closed Caption bit 5 Closed Caption bit 6 Closed Caption bit 7 Closed Caption bit 8 Closed Caption bit 9 Closed Caption bit 10 Closed Caption bit 11 Closed Caption bit 12 Closed Caption bit 13 Closed Caption bit 14 Closed Caption bit 15 Closed Caption bit 0 Closed Caption bit 1 Closed Caption bit 2 Closed Caption bit 3 Closed Caption bit 4 Closed Caption bit 5 Closed Caption bit 6 Closed Caption bit 7 Closed Caption bit 8 Closed Caption bit 9 Closed Caption bit 10 Closed Caption bit 11 Closed Caption bit 12 Closed Caption bit 13 Closed Caption bit 14 Closed Caption bit 15
CC-21=1; CC-284=0 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 X X X X X X X X X X X X X X X X
CC21=0; CC-284=1 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 X X X X X X X X X X X X X X X X
CC21=1; CC-284=1 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 21 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284 line 284
LOWER BYTE LOWER MIDDLE BYTE UPPER MIDDLE BYTE UPPER BYTE
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Note: A31 is MSB
Table 7. Closed Caption (CC) Register Summary
23
ML6460
FUNCTIONAL DESCRIPTION
PRESET PIN CONTROL The ML6460 can be controlled by a pair of preset mode pins. These pins do not allow access to all of the programmable features of the ML6460, but are intended to provide a simpler interface for most applications. Refer to Table 8 for preset modes. SERIAL BUS OPERATION The serial bus control in the ML6460 has two levels of addressing: Device Addressing and Functional Addressing. Device Addressing: Figures 15, 16, and 17 show the physical waveforms generated in order to address the ML6460. There are six basic parts of the waveform: Start Indication: Clock Cycle 0 Device Address Shifted in: Clock Cycle 1 through 8 Device Address Strobed and Decoded: Clock Cycle 9 Function Address Shifted in: Clock Cycle 10 through 17 Function Address Strobed and Decoded: Clock Cycle 18 Data Shifted in 8 bits at a time, MSB first: Clock Cycle 19 through 26 7. Data Shifted: Clock Cycle 27 8. Repeat strep 6 & 7 until all data is clocked in. 9. Stop indication: After Last Clock Cycle (54 for CC, 54 for CNTR) Note: data at SDATA is ignored at steps 3, 5, and 7. Device & Function Addressing: Figures 15, 16, an17 show the register address procedure of the ML6460. 1. 2. 3. 4. 5. 6. (Continued) Device Address (8 bit) 1011 0100 (Hex = B4) Function Address (8 bit) Closed Caption Data Registers (CC): 0000 0000 (Hex = 00) Macrovision Control Registers (CPC): confidential Macrovision Data Registers (CPS): confidential Control Registers (CNTR): 0000 0011 (Hex = 03) Number of Data Bits Closed Caption Data Registers (CC): 4 x 8 bits Macrovision Control Registers (CPC): confidential Macrovision Data Registers (CPS): confidential Control Registers (CNTR): 4 x 8 bits CONTROL REGISTER DEFAULT SETTINGS At Power up, the ML6460 default settings are as follows: * Control Register is undefined when the serial bus mode is enabled. * Macrovision Register is automatically configured by the Macrovision default values. * Chip is ready to process video * Preset Pins are available and if used will configure the control register. * Must write logic "0" (zero) to A30 to get video To get black at power up will require logic "1" in A30.
MODE PRESET1
PRESET0
CC XX XX XX XX
CNTR XXXXXXXX 09080209 1C080209 11080209
CPC * * * *
CPS * * * *
A 0 0 B 0 1 C 1 0 D 1 1 X = don't care * = confidential information Mode Description
Mode A: All register contents are programmed through serial interface. Mode B: Master mode, CCIR656 rate, analog blanking. Mode C: Slave mode, SAV and EAV codes, CCIR656 rate, digital blanking. Mode D: Slave mode, external sync at start of line, Square pixel rate, analog blanking
Table 8. Preset Modes and Register Values
24
ML6460
START SDATA tRISE All Other SDATA Transitions Must Occur While SCLK is Low tSET/START SCLK START: A Falling Edge on the SDATA While SCLK is Held High STOP: A Rising Edge on the SDATA While SCLK is Held High STOP tFALL
Figure 15. Definition of START & STOP on Serial Data Bus
START SDATA MSB A7 A6
DEVICE ADDRESS MSB A1 A0 X A7 A6
FUNCTION ADDRESS
A1
A0
X
SCLK 0 1 2 7 8 9 10 11 16 17 18
SCLK: SCLK: SCLK: SCLK: SCLK:
9th pulse strobes dummy bit for ACK Rising edge enables data transfer Falling edge disables data transfer Rising edge enables data transfer Falling edge in prep for first address transfer
SCLK: SCLK: SCLK: SCLK:
9th pulse strobes dummy bit for ACK Rising edge enables data transfer Falling edge disables data transfer Rising edge enables data transfer
SDATA: Value set to A6, Device Address (MSB-1)
SDATA: Value set to D6, Data MSB-1
SDATA: Value set to A7, Device Address MSB SDATA; Falling edge with SCLK Hi means start of sequence
SDATA: Value set to D7, Data MSB
Figure 16. Definition of ADDRESS FORMAT on Serial Data Bus
25
ML6460
SDATA FROM DEVICE AND FUNCTION X ADDRESS
MSB BIT 31
BIT 30
BIT 24
X
BIT 23
BIT 16
X
BIT 15
BIT 8
X
BIT 7
LSB BIT 0
X
STOP
19
20
26
27
28
35
36
37
44
45
46
53
54
Pulse Strobes Dummy Bit for ACK UPPER BYTE
UPPER MIDDLE BYTE
LOWER MIDDLE BYTE
LOWER BYTE
CLOSED CAPTION REGISTER
MSB
CONTROL REGISTER UPPER BYTE
MSB
UPPER BYTE B29 B28 B27 B26 B25 B24 X
A31
A30
A29 A28
A27
A26
A25 A24
X
B31
B30
UPPER MIDDLE BYTE A23 A22 A21 A20 A19 A18 A17 A16 X B23 B22
UPPER MIDDLE BYTE B21 B20 B19 B18 B17 B16 X
LOWER MIDDLE BYTE A15 A14 A13 A12 A11 A10 A9 A8 X B15 B14
LOWER MIDDLE BYTE B13 B12 B11 B10 B9 B8 X
LOWER BYTE A7 A6 A5 A4 A3 A2 A1 A0
LSB
LOWER BYTE B7 B6 B5 B4 B3 B2 B1 B0
LSB
X
X
X = DUMMY BIT
X = DUMMY BIT
Figure 17. Register Organization and Timing
26
ML6460
TYPICAL APPLICATIONS
DVD DISK
DATA FROM SERVO
COPY PROTECTION
MPEG-2 VIDEO DECODER
16MB SDRAM VIDEO ANALOG OUT CV YCrCb ML6460 OR ML6461
MPEG2 VIDEO OUT
VIDEO PROCESSOR
Y C
AC-3 I/F
AC-3 DECODER
AUDIO OUT
AUDIO ANALOG OUT
Figure 18. Typical Encoding Application (DVD Systems)
BNC
COMPOSITE VIDEO RS - 170 VIDEO DECODER
MINI DIN
Y/C S-VHS
CV
PCI BUS
PCI CONTROLLER
WAVELET COMPRESSION
YCrCb
ML6460 OR ML6461
Y C
VIDEO ANALOG OUT
Figure 19. Typical Encoding Application (Low Cost Video Capture or Camera Systems)
27
ML6460
TYPICAL APPLICATIONS
DAUGHTER CARD CAMCORDER OR VCR VIDEO DECODER DVD YcRcB ML6460 ML6461 ENCODER CV Y C
RGB
VMI/VIP PORT YCrCb
RGB MONITOR
3D GRAPHICS PROCESSOR
AGP OR PCI CONNECTOR
Figure 20. Typical Encoding Application (PC/TV DVD on Graphics Card)
RF DEMODULATOR TERRESTRIAL SIGNAL CV
GENLOCK OVERLAY PROCESSOR
ALPHAKEY
FADER
Y/C
ANALOG
MPEG2 DECODER OSD ALPHAKEY MPEG VIDEO DECODER YUV NTSC/PAL ENCODER
ANALOG
CV
BANDSPLIT
CV
Y/C AGC
SYNC SEPARATOR/ GENLOCK
DIGITAL
ML6460 ML6461 NTSC ENCODER
Y/C
CHROMA LOCK
Figure 21. Typical Encoding Application (MPEG2/Overlay Systems)
28
ML6460
R525 75
C520 220F
S VIDEO
R524 75
C519 220F
ML6460
R521 470k D1 1N4148 1 2 3 4 C304 1F VCC 5 6 7 8 NC NC 9 10 11 12 13 14 Y0--Y7 AVCC1 AGND1 PRESET0 PRESET1 FIELD PHERR DVCC1 DGND1 VSYNC HSYNC YCRCB7 YCRCB6 YCRCB5 DVCC2
U301
COUT YOUT CVOUT AVCC2 AGND2 SDATA SCLK YCRCB0 YCRCB1 YCRCB2 YCRCB3 YCRCB4 CLK DGND2
28 27 26 25 24 23 22 21 20 19 18 17 16 15 C302 0.1F FB301 FERRITE BEAD VCC R523 75 C518 220F
RCA J302
CVOUT
C030 47F
CLK SCL SDA
Figure 22. Typical Application Schematic
29
ML6460
PHYSICAL DIMENSIONS
inches (millimeters)
Package: S28 28-Pin SOIC
0.699 - 0.713 (17.75 - 18.11)
28
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES)
0.050 BSC (1.27 BSC)
0.095 - 0.107 (2.41 - 2.72)
0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER ML6460CS MACROVISION(R) YES TEMPERATURE RANGE 0C to 70C PACKAGE 28 Pin SOIC (S28)
(c) Micro Linear 1999.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
DS6460-01
30

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